In the fabrication of integrated circuits and other electronic devices, multiple layers of conducting, semiconducting and dielectric materials are deposited on or removed from a surface of a semiconductor wafer. Thin layers of conducting, semiconducting, and dielectric materials can be deposited by several deposition techniques. Common deposition techniques in modem processing include physical vapor deposition (PVD), also known as sputtering, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), and electrochemical plating (ECP).
As layers of materials are sequentially deposited and removed, the uppermost surface of the wafer becomes non-planar. Because subsequent semiconductor processing (e.g., metallization) requires the wafer to have a flat surface, the wafer needs to be planarized. Planarization is useful in removing undesired surface topography and surface defects, such as rough surfaces, agglomerated materials, crystal lattice damage, scratches, and contaminated layers or materials.
Chemical mechanical planarization, or chemical mechanical polishing (CMP), is a common technique used to planarize substrates, such as semiconductor wafers. In conventional CMP, a wafer is mounted on a carrier assembly and positioned in contact with a polishing pad in a CMP apparatus. The carrier assembly provides a controllable pressure to the wafer, pressing it against the polishing pad. The pad is moved (e.g., rotated) relative to the wafer by an external driving force. Simultaneously therewith, a polishing composition (“slurry”) or other polishing solution is provided between the wafer and the polishing pad. Thus, the wafer surface is polished and made planar by the chemical and mechanical action of the pad surface and slurry.
In front-end-of-line (FEOL) semiconductor processing, shallow trench isolation (STI) is critical to the formation of gates in integrated circuit fabrication, such as prior to formation of the transistors in STI, a dielectric such as tetraethyl orthosilicate (TEOS) or silicon dioxide is deposited in excess in openings formed in the silicon wafer, for example, a trench or isolation area which is isolated from the remainder of the integrated circuit by silicon nitride barrier. Multiple CMP processes are used to achieve a final desired isolation scheme. In the first CMP step, excess dielectric is polished and planarized. In the second CMP step, polish stop is achieved on underlying silicon nitride film without excessive dishing (oxide loss in the trench). In the third CMP step, which is relatively new or being implemented in advanced semiconductor devices, both oxide and nitride are polished and CMP stop is achieved on underlying silicon films, such as amorphous silicon films.
Accordingly, the present invention is directed to a chemical mechanical polishing composition and method for improving the third step by polishing both the oxide and nitride and suppressing the removal rate of amorphous silicon.